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cy62128e mobl ? 1-mbit (128 k 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05485 rev. *k revised june 3, 2013 1-mbit (128 k 8) static ram features very high speed: 45 ns temperature ranges ? industrial: ?40 c to +85 c ? automotive-a: ?40 c to +85 c ? automotive-e: ?40 c to +125 c voltage range: 4.5 v to 5.5 v pin compatible with cy62128b ultra low standby power ? typical standby current: 1 ? a ? maximum standby current: 4 ? a (industrial) ultra low active power ? typical active current: 1.3 ma at f = 1 mhz easy memory expansion with ce 1 , ce 2, and oe features automatic power down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power offered in standard pb-free 32-pin stsop, 32-pin soic, and 32-pin thin small outline package (tsop) type i packages functional description the cy62128e is a high perf ormance cmos static ram organized as 128k words by 8 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications. the device also has an automatic power down feature that significantly re duces power consumption when addresses are not toggling. placing the device into standby mode reduces power consumption by more than 99 percent when deselected (ce 1 high or ce 2 low). the eight input and output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce 1 high or ce 2 low), the outputs are disabled (oe high), or a write operation is in progress (ce 1 low and ce 2 high and we low) to write to the device, take chip enable (ce 1 low and ce 2 high) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 16 ). to read from the device, take chip enable (ce 1 low and ce 2 high) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins appear on the i/o pins. the cy62128e device is suitable for interfacing with processors that have ttl i/p levels. it is no t suitable for processors that require cmos i/p levels. please see electrical characteristics on page 5 for more details and suggested alternatives. logic block diagram a 0 i/o 0 i/o 7 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 12 sense amps power down we oe a 13 a 14 a 15 a 16 row decoder column decoder 128k x 8 array input buffer a 10 a 11 ce 1 ce 2 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7
cy62128e mobl ? document number: 38-05485 rev. *k page 2 of 19 contents pin configuration ............................................................. 3 product portfolio .............................................................. 4 maximum ratings ............................................................. 5 operating range ............................................................... 5 electrical characteristics ................................................. 5 capacitance ...................................................................... 6 thermal resistance .......................................................... 6 ac test loads and waveforms ....................................... 6 data retention characteristics ....................................... 7 data retention waveform ................................................ 7 switching characteristics ................................................ 8 switching waveforms ...................................................... 9 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagrams .......................................................... 13 acronyms ........................................................................ 16 document conventions ................................................. 16 units of measure ....................................................... 16 document history page ................................................. 17 sales, solutions, and legal information ...................... 19 worldwide sales and design s upport ......... .............. 19 products .................................................................... 19 psoc solutions ......................................................... 19
cy62128e mobl ? document number: 38-05485 rev. *k page 3 of 19 pin configuration figure 1. 32-pin stsop pinout [1] figure 2. 32-pin tsop i pinout [1] figure 3. 32-pin soic pinout [1] a 6 a 7 a 16 a 14 a 12 we v cc a 4 a 13 a 8 a 9 oe stsop top view (not to scale) 30 28 29 31 24 19 23 22 21 20 18 13 17 16 15 14 11 12 i/o 2 i/o 1 gnd i/o 7 i/o 4 i/o 5 i/o 6 i/o 0 ce 1 a 11 a 5 9 10 32 1 2 3 4 5 6 7 8 ce 2 a 15 nc a 10 i/o 3 a 1 a 0 a 3 a 2 26 25 26 27 8 9 10 11 14 12 13 16 15 21 22 19 20 25 17 18 23 24 a 11 a 10 4 a 3 a 2 a 1 a 0 /o 0 /o 1 o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 v ss oe ce 1 a 6 a 7 a 16 a 14 a 12 we v cc a 4 a 13 a 8 a 9 oe tsop i top view (not to scale) 1 6 2 3 4 5 7 32 27 31 30 29 28 26 21 25 24 23 22 19 20 i/o 2 i/o 1 gnd i/o 7 i/o 4 i/o 5 i/o 6 i/o 0 ce 1 a 11 a 5 17 18 8 9 10 11 12 13 14 15 16 ce 2 a 15 nc a 10 i/o 3 a 1 a 0 a 3 a 2 1 2 3 4 5 6 7 31 32 29 30 27 28 26 32-pin soic top view c 16 a 15 14 a 13 12 a a 9 a 8 a 7 a 6 a 5 a v cc ce 2 we a 16 a 14 we v cc a 13 a 8 a 9 stsop top view (not to scale) 30 28 29 31 a 11 32 1 2 3 ce 2 a 15 nc 26 25 26 27 a 6 a 7 a 16 a 14 a 12 we v cc a 4 a 13 a 8 tsop i top view (not to scale) 6 3 4 5 7 a 5 8 9 10 11 12 13 14 15 16 ce 2 a 15 nc 1 2 3 4 5 6 7 8 9 10 11 14 31 32 12 13 16 15 29 30 21 22 19 20 27 28 25 26 17 18 23 24 top view top view nc a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 v ss v cc ce 2 we oe ce 1 note 1. nc pins are not connected on the die.
cy62128e mobl ? document number: 38-05485 rev. *k page 4 of 19 product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 (a) f = 1mhz f = f max min typ [2] max typ [2] max typ [2] max typ [2] max cy62128ell industrial / automotive-a 4.5 5.0 5.5 45 [3] 1.3 2 11 16 1 4 cy62128ell automotive-e 4.5 5.0 5.5 55 1.3 4 11 35 1 30 notes 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 3. when used with a 100 pf capacitive load and resistive loads as shown on page 4, access times of 55 ns (t aa , t ace ) and 25 ns (t doe ) are guaranteed.
cy62128e mobl ? document number: 38-05485 rev. *k page 5 of 19 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage to ground potential ........................... ?0.5 v to 6.0 v (v cc(max) + 0.5 v) dc voltage applied to outputs in high z state [4, 5] .......... ?0.5 v to 6.0 v (v cc(max) + 0.5 v) dc input voltage [4, 5] ........ ?0.5 v to 6.0 v (v cc(max) + 0.5 v) output current into outputs (low) ............................. 20 ma static discharge voltage (mil-std-883, method 3015) ................................. > 2001 v latch up current ..................................................... > 200 ma operating range device range ambient temperature v cc [6] cy62128ell industrial / automotive-a ?40 c to +85 c 4.5 v to 5.5 v automotive-e ?40 c to +125 c electrical characteristics over the operating range parameter description test conditions 45 ns (industrial/ automotive-a) 55 ns (automotive-e) unit min typ [7] max min typ [7] max v oh output high voltage v cc = 4.5 v i oh = ?1 ma 2.4 ? ? 2.4 ? ? v v cc = 5.5 v i oh = ?0.1 ma ? ? 3.4 [8] ? ? 3.4 [8] v ol output low voltage i ol = 2.1 ma ? ? 0.4 ? ? 0.4 v v ih input high voltage v cc = 4.5 v to 5.5 v 2.2 ? v cc + 0.5 2.2 ? v cc + 0.5 v v il input low voltage v cc = 4.5 v to 5.5 v ?0.5 ? 0.8 ?0.5 ? 0.8 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ?4 ? +4 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ?4 ? +4 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels ?11 16 ?11 35 ma f = 1 mhz ? 1.3 2 ? 1.3 4 i sb2 [9] automatic ce power-down current?cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc(max) ?1 4 ?1 30 ? a notes 4. v il(min) = ?2.0 v for pulse durations less than 20 ns. 5. v ih(max) = v cc + 0.75 v for pulse durations less than 20 ns. 6. full device ac operation assumes a 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 7. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 8. please note that the maximum v oh limit doesnot exceed minimum cmos v ih of 3.5 v. if you are interfacing this sram with 5 v legacy processors that require a minimum v ih of 3.5 v, please refer to application note an6081 for technical details and options you may consider. 9. only chip enables (ce 1 and ce 2 ) must be at cmos level to meet the i sb2 / i ccdr spec. other inputs can be left floating.
cy62128e mobl ? document number: 38-05485 rev. *k page 6 of 19 capacitance parameter [10] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [10] description test conditions 32-pin soic package 32-pin stsop package 32-pin tsop package unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 48.67 32.56 33.01 ? c/w ? jc thermal resistance (junction to case) 25.86 3.59 3.42 ? c/w ac test loads and waveforms figure 4. ac test loads and waveforms 3.0 v v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thevenin equivalent all input pulses r th r1 parameters value unit r1 1800 ? r2 990 ? r th 639 ? v th 1.77 v note 10. tested initially and after any design or process changes that may affect these parameters.
cy62128e mobl ? document number: 38-05485 rev. *k page 7 of 19 data retention characteristics over the operating range parameter description conditions min typ [11] max unit v dr v cc for data retention 2 ? ? v i ccdr [12] data retention current v cc = v dr , ce 1 > v cc ?? 0.2 v or ce 2 < 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v industrial / automotive-a ??4 ? a automotive-e ? ? 30 ? a t cdr [13] chip deselect to data retention time 0??ns t r [14] operation recovery time cy62128ell-45 45 ? ? ns cy62128ell-55 55 ? ? data retention waveform figure 5. data retention waveform [15] v cc(min) v cc(min) t cdr v dr > 2.0 v data retention mode t r v cc ce notes 11. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 12. only chip enables (ce 1 and ce 2 ) must be at cmos level to meet the i sb2 / i ccdr spec. other inputs can be left floating. 13. tested initially and after any design or proces s changes that may affect these parameters. 14. full device ac operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) > 100 s. 15. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high.
cy62128e mobl ? document number: 38-05485 rev. *k page 8 of 19 switching characteristics over the operating range parameter [16] description 45 ns (industrial / automotive-a) 55 ns (automotive-e) unit min max min max read cycle t rc read cycle time 45?55?ns t aa address to data valid ? 45 ? 55 ns t oha data hold from address change 10 ? 10 ? ns t ace ce 1 low and ce 2 high to data valid ? 45 ? 55 ns t doe oe low to data valid ? 22 ? 25 ns t lzoe oe low to low z [17] 5? 5 ?ns t hzoe oe high to high z [17, 18] ?18? 20 ns t lzce ce 1 low and ce 2 high to low z [17] 10 ? 10 ?ns t hzce ce 1 high or ce 2 low to high z [17, 18] ?18? 20 ns t pu ce 1 low and ce 2 high to power-up 0 ? 0 ?ns t pd ce 1 high or ce 2 low to power-down ? 45 ? 55 ns write cycle [19] t wc write cycle time 45 ? 55 ? ns t sce ce 1 low and ce 2 high to write end 35 ? 40 ?ns t aw address setup to write end 35 ? 40 ? ns t ha address hold from write end 0 ? 0 ?ns t sa address setup to write start 0 ? 0 ? ns t pwe we pulse width 35 ? 40 ?ns t sd data setup to write end 25 ? 25 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe we low to high z [17, 18] ?18? 20 ns t lzwe we high to low z [17] 10 ? 10 ?ns notes 16. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 3 ns (1 v/ns) or less, t iming reference levels of 1.5 v, input pulse levels of 0 to 3 v, and output loading of the specified i ol /i oh as shown in the figure 4 on page 6 . 17. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 18. t hzoe , t hzce , and t hzwe transitions are measured when the outputs enter a high impedance state. 19. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the signal that terminates th e write.
cy62128e mobl ? document number: 38-05485 rev. *k page 9 of 19 switching waveforms figure 6. read cycle 1 (address transition controlled) [20, 21] figure 7. read cycle no. 2 (oe controlled) [21, 22, 23] figure 8. write cycle no. 1 (we controlled) [23, 24, 25, 26] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd impedance i cc i sb high address ce data out v cc supply current oe data valid t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe address ce we data i/o oe note 27 notes 20. the device is continuously selected. oe , ce 1 = v il , ce 2 = v ih . 21. we is high for read cycle. 22. address valid before or similar to ce 1 transition low and ce 2 transition high. 23. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 24. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the signal that ter minates the write. 25. data i/o is high impedance if oe = v ih . 26. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in high impedance state. 27. during this period, the i/os are in output state and input signals must not be applied.
cy62128e mobl ? document number: 38-05485 rev. *k page 10 of 19 figure 9. write cycle no. 2 (ce 1 or ce 2 controlled) [28, 29, 30, 31] figure 10. write cycle no. 3 (we controlled, oe low) [28, 31] switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce address ce data i/o we data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe address ce we data i/o note 32 notes 28. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 29. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the signal that ter minates the write. 30. data i/o is high impedance if oe = v ih . 31. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in high impedance state. 32. during this period, the i/os are in output state and input signals must not be applied.
cy62128e mobl ? document number: 38-05485 rev. *k page 11 of 19 truth table ce 1 ce 2 we oe inputs/outputs mode power hx [33] x x high z deselect/power down standby (i sb ) x [33] l x x high z deselect/power down standby (i sb ) l h h l data out read active (i cc ) l h l x data in write active (i cc ) l h h h high z selected, outputs disabled active (i cc ) note 33. the ?x? (don?t care) state for the chip enables in the truth table refer to the logic state (either high or low). intermedia te voltage levels on these pins is not permitted.
cy62128e mobl ? document number: 38-05485 rev. *k page 12 of 19 ordering information speed (ns) ordering code package diagram package type operating range 45 CY62128ELL-45SXI 51-85081 32-pin 450-mil soic (pb-free) industrial cy62128ell-45zaxi 51-85094 32-pin stsop (pb-free) cy62128ell-45zxi 51-85056 32-pin tsop type i (pb-free) cy62128ell-45sxa 51-85081 32-pin 450 -mil soic (pb-free) automotive-a cy62128ell-45zxa 51-85056 32-pin tsop type i (pb-free) 55 cy62128ell-55sxe 51-85081 32-pin 450 -mil soic (pb-free) automotive-e cy62128ell-55zaxe 51-85094 32-pin stsop (pb-free) contact your local cypress sales repres entative for availability of these parts. ordering code definitions temperature grade: x = i or a or e i = industrial; a = automo tive-a; e = automotive-e pb-free package type: xx = s or za or z s = 32-pin soic za = 32-pin stsop z = 32-pin tsop type i speed grade: xx = 45 ns or 55 ns ll = low power e = process technology 90 nm bus width = 8 density = 1-mbit family code: mobl sram family company id: cy = cypress cy xx xx 621 2 8 x ll x - e
cy62128e mobl ? document number: 38-05485 rev. *k page 13 of 19 package diagrams figure 11. 32-pin molded soic (450 mil) s32.45/sz32.45 package outline, 51-85081 51-85081 *e
cy62128e mobl ? document number: 38-05485 rev. *k page 14 of 19 figure 12. 32-pin small tsop (8 13. 4 1.2 mm) za32 package outline, 51-85094 package diagrams (continued) 51-85094 *f
cy62128e mobl ? document number: 38-05485 rev. *k page 15 of 19 figure 13. 32-pin tsop i (8 20 1.0 mm) z32, 51-85056 package diagrams (continued) 51-85056 *f
cy62128e mobl ? document number: 38-05485 rev. *k page 16 of 19 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory soic small outline integrated circuit stsop small thin small outline package tsop thin small outline package we write enable symbol unit of measure c degree celsius mhz megahertz ? a microampere ? s microsecond ma milliampere mm millimeter ns nanosecond ? ohm % percent pf picofarad v volt w watt
cy62128e mobl ? document number: 38-05485 rev. *k page 17 of 19 document history page document title: cy62128e mobl ? , 1-mbit (128 k 8) static ram document number: 38-05485 rev. ecn no. submission date orig. of change description of change ** 203120 see ecn aju new data sheet *a 299472 see ecn syt converted from advance information to preliminary changed t oha from 6 ns to 10 ns for both 35 ns and 45 ns, respectively changed t doe from 15 ns to 18 ns for 35 ns speed bin changed t hzoe , t hzwe from 12 and 15 ns to 15 and 18 ns for the 35 and 45 ns speed bins, respectively changed t hzce from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns speed bins, respectively changed t sce from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns speed bins, respectively changed t sd from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns speed bins, respectively added pb-free package information added footnote #9 changed operating range for soic package from commercial to industrial modified signal transition time from 5 ns to 3 ns in footnote #11 changed max of i sb1 , i sb2 and i ccdr from 1.0 ? a to 1.5 ? a *b 461631 see ecn nxr converted from preliminary to final included automotive range and 55 ns speed bin removed 35 ns speed bin removed ?l? version of cy62128e removed reverse tsop i package from product offering changed i cc (typ) from 8 ma to 11 ma and i cc (max) from 12 ma to 16 ma for f = f max changed i cc (max) from 1.5 ma to 2.0 ma for f = 1 mhz removed i sb1 dc specs from electrical characteristics table changed i sb2 (max) from 1.5 ? a to 4 ? a changed i sb2 (typ) from 0.5 ? a to 1 ? a changed i ccdr (max) from 1.5 ? a to 4 ? a changed the ac test load capacitance value from 100 pf to 30 pf changed t lzoe from 3 to 5 ns changed t lzce from 6 to 10 ns changed t hzce from 22 to 18 ns changed t pwe from 30 to 35 ns changed t sd from 22 to 25 ns changed t lzwe from 6 to 10 ns updated the ordering information table *c 464721 see ecn nxr updated the block diagram on page # 1 *d 563144 see ecn aju added footnote 4 on page 2 *e 1024520 see ecn vkn added automotive-a information converted automotive-e specs to final added footnote #9 related to i sb2 and i ccdr updated ordering information table *f 2548575 08/05/08 nxr corrected typo error in ordering information table *g 2934396 06/03/10 vkn added footnote #22 related to chip enable updated package diagrams updated template *h 3113780 12/17/2010 pras updated logic block diagram. added ordering code definitions.
cy62128e mobl ? document number: 38-05485 rev. *k page 18 of 19 *i 3223635 04/12/2011 rame updated as per new template removed v30 value from ordering code definition. added acronyms and units of measure table updated package diagram 51-85056 from *e to *f and 51-85094 *e to *f *j 3292276 06/24/2011 rame updated data retention characteristics (changed the conditions and minimum value of t r parameter). updated in new template. *k 4018425 06/03/2013 memj updated functional description . updated electrical characteristics : added one more test condition ?v cc = 5.5 v, i oh = ?0.1 ma? for v oh parameter and added maximum value corresponding to that test condition. added note 8 and referred the same note in maximum value for v oh parameter corresponding to test condition ?v cc = 5.5 v, i oh = ?0.1 ma?. updated package diagrams : spec 51-85081 ? changed revision from *c to *e. completing sunset review. document history page (continued) document title: cy62128e mobl ? , 1-mbit (128 k 8) static ram document number: 38-05485 rev. ecn no. submission date orig. of change description of change
document number: 38-05485 rev. *k revised june 3, 2013 page 19 of 19 all products and company names mentioned in this document may be the trademarks of their respective holders. cy62128e mobl ? ? cypress semiconductor corporation, 2004-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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